The present invention relates to a semiconductor memory device, and more particularly, to a non-volatile semiconductor memory device capable of performing a stable write operation.
A conventional electrically erasable programmable ROM (EEPROM) contains memory cells including a plurality of transistors each having a double structure of a floating gate and a control gate. Data is written into a memory cell transistor by causing hot electrons produced in the drain region of the floating gate to be accelerated into the source region thereof with part of the accelerated electrons injected into the floating gate. Data is read from the cell by detecting a change in the operating characteristic of the memory cell transistor, which depends on the amount of change injected into the floating gate. In other words, a data read operation takes place by detecting a change in the threshold value of the memory cell transistor.
Referring to FIG. 1, a conventional semiconductor memory device 100 will now be described. The memory device 100 comprises a plurality of memory cell transistors 1 arranged in four rows and one column, and a row decoder 6 connected to the memory cell transistors 1. In FIG. 1, a column select circuit is omitted from the illustration.
Each memory cell transistor 1 comprises an electrically isolated floating gate and which stores a charge, a control gate partly overlapping the floating gate, a source region and a drain region. The memory cell transistors 1 are turned on/off in accordance with a potential applied to the control gates. Each memory cell transistor 1 has a threshold value which varies depending on the amount of charge stored on the floating gate. Two adjacent memory cell transistors form a pair.
A word line 2 is associated with each row of memory cell transistors, and interconnects the control gate of each memory cell transistor 1 and the row decoder 6. A bit line 3 is disposed in a manner corresponding to the column of memory cell transistors 1. The bit line 3 is connected to the drains of respective memory cell transistors 1 and is connected to a current control transistor 5. A source line 4 is connected to the sources of each pair of adjacent memory cell transistors 1. During a write operation, a write potential Vp is applied to the source of each memory cell transistor 1 via the source line 4.
The current control transistor 5 has a source connected to the bit line 3, a drain connected to ground, and a gate. The current control transistor 5 controls the amount of a write-in current ip which flows from the bit line 3 to the ground in accordance with a gate potential Vci. During the write operation, the potential Vp is applied to the source of the memory cell transistor 1 via the source line 4. When the current control transistor 5 is turned on in response to the gate potential Vci, the bit line 3 is connected to the ground via the current control transistor 5. The write-in current ip then passes via a selected one of the memory cell transistors 1. The current control transistor 5 maintain the amount of the write-in current ip constant.
The row decoder 6 receives row address information from a control circuit, not shown, and operates one of row select signals LS1 to LS4, which activates a corresponding one of the four word lines 2. The row decoder 6 supplies the row select signals LS1-LS4 to the associated word line 2 in response to a select clock .phi.c. In this manner, one of the memory cell transistors 1 which is connected to the activated word line 2 is turned on.
While only one column of memory cell transistors 1 is shown in FIG. 1, it should be understood that the memory cell transistors 1 may be arranged to form a plurality of columns. In such instance, a column decoder, not shown, selects one of the columns in accordance with column address information. Subsequently, one of the plurality of memory cell transistors 1 located within the selected column is selected in accordance with the row address information.
The select clock .phi.c is produced or rises when address information is switched. As shown in FIG. 2, the select clock .phi.c includes a first interval P1 at which time the address information is switched and a second interval P2 when a write operation with respect to the memory cell transistor 1 takes place. In the first interval P1, the row select signals LS1 to LS4 establish a non-select condition of all the memory cell transistors until the switching of address information is completed. In the meantime, the bit line 3 is maintained electrically floating. The current control transistor 5 is turned on in response to the gate potential Vci. In the second interval P2, one of the row select signals LS1 to LS4 rises to select one of the memory cell transistors 1 in accordance with the address information which has been completely switched. The write-in current ip then passes from the source line 4 to the bit line 3 via the selected one of the memory cell transistors 1.
In FIG. 2, a solid line indicates a change in the bit line potential VBL when the floating gate of the memory cell transistor 1 is not charged, and broken lines indicate a corresponding change when the floating gate of the memory cell transistor 1 is charged. When the potential of the floating gate of the memory cell transistor 1 is at the ground potential, the bit line potential VBL gradually rises with a flow of the write-in current ip. After a predetermined time interval passes, the potential VBL converges to a potential which is determined by the ratio of the drive capabilities of the memory cell transistor 1 and the current control transistor 5.
The write-in amount or the amount of charge injection into the memory cell transistor 1 is determined by the magnitudes of the write-in potential Vp and the write-in current ip and the interval during which the write-in current ip is allowed to pass. Accordingly, to achieve a stable write operation, it is preferred that the interval of the write operation be controlled accurately and that during the write-in interval, the write-in potential Vp and the write-in current ip be maintained constant.
However, it can be seen from FIG. 2 that if the bit line potential VBL is as low as close to the ground potential, there is a significant potential difference between the source line 4 and the bit line 3 at the commencement of the write operation. This causes a momentary increase in the write-in current ip which passes via the memory cell transistor 1. The momentary increase of the write-in current ip leads to an unstable write operation with respect to the memory cell transistor 1, occasionally causing a variation in the write-in amount. In particular, when driving the semiconductor memory device 100 at a low voltage or when multi-state data is to be written into the memory cell transistor 1, a variation in the write-in amount is likely to cause a write-in error.
It is an object of the invention to provide a semiconductor memory device which enables a stable write operation with respect to a memory cell transistor.